Curriculum Vitae

Petr Vicherek

EDUCATION:

1982 - 1987 Technical University of Brno, Faculty of Electrical Engineering
Major : Microelectronics
Thesis: Digital Filtering of Acoustic Signals.
(Algorithm and HW design of 12-th octave, 8 octaves filter bank, VME bus)

TRAINING COURSES:

• TI DSP seminar on TMS320C240 and TMS320C2xx family.

• ARM processor architecture and ARM tools.

PUBLICATION ACTIVITY:

• 1987 Seminar on Digital Processing - 2 lectures
  1. Effect of fixed point arithmetic on filter behavior
  2. Comparison and evaluation of DSP architectures

• http://petr.vicherek.com/DSPTips.html

AREAS OF EXPERIENCE:

Software

• Fixed Point DSP algorithm analysis, design and implementation

• Accelerated DSP flow algebraic analysis aiding rapid algorithm development.

• Real-time embedded system multiprocessor and multitasking software

• DSP algorithms implemented on inexpensive, General-Purpose Microcontrollers.

• Object oriented, GUI software

• Assembly language, C and C++ real-time systems

Hardware

• Precision analog signal processing and mixed signal processing

• DSP hardware, High speed Digital systems, PALs and FPGAs

• General-purpose microcontrollers, microprocessor systems and peripherals

ACHIVEMENTS:

• Algorithm speed-up by factors of 3 to 70

• Improvements of system throughput by factors between 4 and 100.

• Many improvements in THD, SNR and noise floor between 10 and 60dB

• Reductions in the HW costs, digital and analog from 30% up to 95%

• Developed new algorithms that turned hopeless projects to successful ones

• Successful in removing all hidden instabilities and undesirable artifacts.

• Shortened the development up to half the planned time.

• Building an open, creative and friendly atmosphere in the design team.

CAREER ORIENTATION:

Increase number of achievements, add more to my portfolio of mastered disciplines and techniques and be increasingly more productive in every field of DSP algorithm design and implementation.

SKILLS:

WORK EXPERIENCE :

Oct. 2001 - Present: Eaton Corporation, Rochester Hills, Michigan.  DSP system analyst.

• Precision Impedance Measurement Changed conventional methods to Fourier Transform on 8-bit µP and R-2R DAC to integrating DAC driven by ternary code. Ten-fold increase in accuracy, three-fold reduction of analog front-end in HW complexity and hardware costs. System error analysis, DSP algorithm design, firmware in C and optimization in Assembler and testing.

• Occupant Sensing System  Image processing using ADI SHARC floating point DSP, control by HC12. Image processing DSP algorithm implementation, interprocessor communications, Test scripts for verification. Leading group of firmware engineers develop to robust product ahead of schedule. Analysis, design, simulation, training, implementation, field testing, support.

Jan. 2001 - Oct. 2001: Phillips Semiconductors, Nat.Lab, Eindhoven, The Netherlands.  DSP algorithms.

• Generic DSP Libraries  supporting 24-bit R.E.A.L platform. Several FIR implementations optimized for speed or space, IIR in direct, linear, Gold&Rader, Zölzer and other forms, LMS adaptive FIR, Hilbert Transformer, Windowing, Vector operations, function approximation via Chebyshev polynomials. Every function was implemented both in DSP-C and in assembly, DSP-C usable on both host or on target DSP. Optimizing routines for BDTI benchmarking.

Feb. 98 - Dec. 2000: Ericsson Mobile Networks, Enschede, Netherlands.  DSP algorithms and SW.

• WCDMA processing Real-Time Multithreaded Embedded DSP SW, 3GPP systems on TMS320C6203. System analysis, algorithm design, implementation of decoding algorithms and communication protocols. Improved unit capacity from 20 channels to over 200 with half the board space.

• DSP Libraries for connection of a base station to an analog telco line using DSP Groups OAK architecture. Voice Compression/Decompression, Echo Cancellation, DTMF generation and detection, progress tone and fax tone detection. Cadence SPW, ARM C, Oak Assembler. ITU G.165, G.711, G.726, Q.24 and ETSI DECT standards.

Nov. 95 - Jan 98: TRW AEG Farmington Hills, Michigan.   DSP algorithms and SW analyst

• Electronics Power Steering, SW design, Fixed point DSP algorithm design and implementation. TMS320C240, Assembler & C, MathCad, MC68HC08, C6808, real-time embedded SW. Three-phase precision position sensing, stabilizing IIR   filter and equalizer, non-linear power assist implemented on TMS320C240 and on MC68HC08 overseer processor. DSP Development strategy using algebraic analysis and static verification using sum of partial differentiations. Formal analysis and static verification used for worst case analysis. Optimized fixed point trigonometric functions.

• Seat Belt Timer Module, System, HW, SW and Algorithm design, Coding and Testing. 68HC05, C, MathCad, acceleration sensing and measurement.

Feb 94 - Oct 95: Hewlett-Packard, North York, Ontario HW & SW design, V&V

• Fiber Channel optical switch. HW design FC Interface card, System Test SW & HW. High speed digital HW design FPGAs: Altera, Orca, Xilinx, TMS320C51, Verilog, Synopsys. JTAG scan chain design, test design, ASIC JTAG simulation and verification. BSDL verification, Verilog, Synopsys, ASIC libraries, core scan.

• Test automation. Test board set for high speed backplane.

Feb. 93 - Jan. 94: Crossbow Electronics, Toronto, HW design, ASP/DSP, testing.

• Satellite TDMA DSN card for voice/modem compression, HW design and test SW. High speed digital and analog telco design. E&M, CODEC, interface, DSP algorithm designs, testing. Parallel processing on array of TMS320C51 DSPs. DTMF detection, Echo cancellation G.165, Assembler, C, Cadence/concept, RTOS. Bellcore TRY 506, T1/E1, CCITT Q.2x, G7xx, O.xx, AT&T standards.

• Digital Audio Studio A/D, D/A board and AES/EBU audio and 32x32 channel switch. Altera PLD, MaxPlus, 68302. 96dB SNR, 0.04%THD on switchable set of analog emphasis and de-emphasis filters, 0.5dB deviation. Precise Op-Amps, distortion free switch, mixed signal design.

May. 90 - Jan. 93: Consultronics Inc., Concord, Ontario SW engineer, DSP algorithms

• Caller ID test set, SW/HW design. Modem quality measurement DSP algorithms (QPSK quadrature decoder), DTMF & call progress detection and measurement. C-message and notch IIR filters. 68HC16, assembler, analog signal path design, numeric algorithms, OOP.

• Near End Crosstalk Noise shaping DSP algorithm design, HW & SW. Implementation of Near End Crosstalk noise shaping filter, consultation. Proposed solution 200 times reduces computational intensity, offers non-DSP SW solution over 17"x9" 15A HW card.

• Broadcasting quality measurement instrument, DSP algorithm redesign and coding on DSP56001, MC68000, C, Assembler, multitasking RTOS, OOP, GUI, graphic algorithms.
  Adaptive windowing on RMS amplitude, phase – improvement on smoothness of dynamic response from 30% down below 0.1% of error (worst case).
  IMD measurement using Complex oscillarors and DFT, sigma-delta techniques – 38dB improvement on range
  Crosstalk: Set of filters going up to -120dB on 12-bit A/D ( and 30dB gain). Decimation, sigma-delta and DFT techniques, correlation, adaptive IIR filters.
  IIR Filter design: C-message, CCIR, Psophometric and notch filters optimized approximation resulted in improvement from 8dB down to 0.1dB of error in 20Hz-10kHz range. Soltion by two 4^th order IIRs cut the computational intensity to the total of 30% of original solution.

Nov. 89 - May 90: IED, Richmond Hill, Ontario HW, Firmware, DSP, testing

• Call routing device, Low power discrete Analog HW, microcontroller SW. CCITT DTMF detection and generation on 68HC11 8-bit offset arithmetic. Low power discrete analog design, call progress tones - DSP detection.

• DTMF generation with 68HC11E2, on unsigned arithmetic without lookup tables (space limitations) only 30% CPU time.

• Remote pulse dialing detection, for a small PBX. Fax and call progress DSP algorithm design. Analog signal path design, correlation and IIR filters. Fax detection DSP on HC11, CVDS voice compression, telco hybrid.

• Call restrictor device, Low power Analog HW design, DTMF DSP algorithm design. Bellcore DTMF detection, Assembler 68HC11, search algorithms, analog design. Discrete transistor analog design, 68HC11. Low drop on line voltage, 68HC11, switching operation at 10uA consumption.

• DTMF detection Bellcore compliant, below 70% CPU time on 68HC11E2 on unsigned arithmetic without lookup tables (space limitations). Also HC05, <80% CPU time. Comparable published examples have 20x higher computational intensity, lover or equal quality, 20x higher consumption, 10x higher cost.

Aug. 89 - Nov. 89: Instrumentation Consulting, Markham, Analog/Digital HW and SW design

• Measurement automation instrument for quadrupole mass spectrometers. HPIB, Analog RF high voltage/Digital HW and PC SW design. OrCAD, Pascal.

Nov. 88 - July 89: Olivetti, Rome, Italy P/A, SW design and maintenance.

• Database system for medical laboratory & ambulance. P/A Multitasking multiprocessor C & MS-BASIC design Xenix & DOS, B-Trieve.

Jan. 87 - Sep. 88: Brno, Czechoslovakia, Research Institute of Measurement Technology.

• Digital Storage Oscilloscope, SW design of display unit and Digital HW design. Fast graphical routines, 8051, OOP. Real-time SW, Analog/Digital HW.

MINOR PROJECTS:

• 32-channel DTMF/MF receiver, Algorithm design, Assembly 2181, MathCad. Only 32% of CPU time. Unlike widely published DTMF algorithms based on Goertzel filters, this algorithm does correctly reject and detect tone over the whole Bellcore frequency, duration, twist and dynamic ranges. Using coefficient reduction and high Parallelization techniques this implementation can handle four times as many channels than conceptually simpler Goertzel filter approach.

• 32-channel DTMF/MF Generator: Algorithm design, Assembly 2181, MathCad. 32 Low distortion DTMF channels generated in only 8% of CPU time. Ten times speed Improvement over other published solutions.

• Optical Character Recognition OCR algorithm of known character set tailored for 8-bit 8051 Microcontroller. Achieving 200cps speed and better than 20ppm error rate on first approach, better than 1ppm on improved algorithm.

• Other algorithms: Speech compression, CVDS, ADPCM, A/u-LAW, Call progress, ANI, Fax ID, sidetone suppression, echo cancellation, temperature control loop, DFT, FIRs, IIRs, Adaptive, complex and unit oscillators, fast converging numeric algorithms, fast graphic algorithms. Group Delay and Quantizing Noise measurements, DSP PLL.

• Other analog designs: Power supply SCR supplies, telco hybrid, gain switching, analog filters, thermocouple interfaces, CVDS interface, data acquisition and mixed signal designs.

• Battery backed DRAM ramdisk, HW , driver SW and CP/M implementation.

• Floppy disk interface card. HW, driver SW. Z80. Low power DRAM design, driver optimization, MS-DOS compatibility, Sharp MZ-800 system.

• High vacuum control unit, Analog/Digital HW, real-time Firmware. Precision compensated temperature sensing, temperature control loop. HW mixed signal design, SS relays, 68HC11 Assembler, Borland C++ & OWL.